The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a storage area such as a random-access-memory (RAM), a register, a latch, or a flip-flop (F/F), which is required to test a data-hold characteristic thereof.
A storage area incorporated in a semiconductor device is often required to retain data stored therein even when a power supply voltage supplied thereto is lowered from a typical value. It is therefore necessary to test a data-hold characteristic of the storage area, i.e., to test whether or not the storage area retains the data stored therein during a power down mode in which a power voltage lower than its typical value is being supplied to the device. In particular, the data-hold characteristic is an important factor for a static random-access-memory (SRAM).
In testing the data-hold characteristic of the SRAM, test data are first written therein under the power supply voltage having a typical value (4.5-5.5 V). The SRAM is then brought into a data-hold mode by reducing the power voltage to a power-down voltage, 2 V for example, with keeping a chip-select (CS) signal taking an inactive high level for a predetermined time period. The power voltage is thereafter returned to the typical value and the SRAM is brought into a data read mode by applying the CS signal of the active low level to read out data therefrom. The data thus read out are compared with the expected data. The test for the data-hold characteristic is thus completed.
Referring to FIG. 9, there is shown a relationship between the power supply voltage and the CS signal for the SRAM as described above. The power supply voltage Vcc is indicated by a line 80, and the CS signal is indicated by a line 81. As described hereinbefore, the CS signal is maintained at the high level during a data-hold period and is changed to the active low level during periods other than the data-hold period to bring the SRAM into a data write mode or a data read mode. In FIG. 9, further, t.sub.CDR is defined as a chip-select set time which represents a time period from a time point at which the chip select signal CS is changed to the high level to a time point at which the power supply voltage Vcc is reduced to the minimum level of the typical power supply voltage. This time period is generally stipulated to be 0 ms in specifications of the data-hold test. On the other hand, t.sub.R is defined as a chip-select hold time which represents a time period from a time point at which the power supply voltage Vcc is returned to reach the level of 4.5 V to a time point at which the chip-select signal CS is changed to the low level. This period is generally stipulated to be 5 ms in the specifications of the data-hold test.
In an actual test, only one SRAM is not tested, but a number of SRAMs are coupled in parallel and tested at a time, as well known in the art. For this reason, test equipment is subjected to drive a very large capacitive load. Moreover, a decoupling capacitor having a large capacitance (for example, 1 .mu.F) is coupled to a power supply line to stabilize the power supply voltage. As a result, it takes a relatively long time period to reduce the power supply voltage to the power-down level or to return it to the typical level. The test time is thus prolonged accordingly.
Furthermore, in the case where each memory cell of the SRAM is of a type having a load resistor of resistance of the order of several teraohms, the change in the actual power voltage applied to the memory cell is further lowered. For this reason, a certain memory cell is allowed to retrieve from the incorrect data storing condition even if it has a degraded drive capability. Such a defect memory cell is not detected consequently.